module top(input clk1,
           input clk2,
           input select,
           input rst_n,
           output clk_out);

reg out1;
reg out2;
assign clk_out = (out1 & clk1) | (out2 & clk2);
always@(negedge clk1 or negedge rst_n)
	begin
		if (!rst_n)
			out1 <= 1'b0;
		else
			out1 <= (~out2) & select;
	end
always@(negedge clk2 or negedge rst_n)
	begin
		if (!rst_n)
			out2 <= 1;
		else
			out2 <= (~out1) & (~select);
	end
endmodule
